The present invention relates to a semiconductor memory device and a method of manufacturing the same.
A currently most advanced random access memory (RAM) is exemplified by dynamic RAMs (to be referred to as 1Tr type dRAMs hereinafter) each having a cell structure consisting of one transistor and one capacitor. Among the 1Tcr type dRAMs, a memory cell structure, in that one bit line contact hole is commonly used for two adjacent cells is most advantageous for increasing the packing density of cells. This 1Tr type dRAM is widely employed.
A typical example is illustrated in FIGS. 1 and 2.
The following description will be made for n-channel MIS dRAMs of the prior art and the present invention. However, a p-channel MIS dRAM can also be prepared in the same manner as in the n-channel MIS dRAM by reversing the conductivity type of the silicon substrate, diffusion layers and a channel stopper and the polarity of the applied voltage. When an epitaxial layer or a well region is formed on a bulk semiconductor substrate, the epitaxial layer or the well region should be treated as the silicon substrate having the same polarity as the epitaxial layer or the well region.
Referring to FIG. 1, a region surrounded by a broken line represents a memory cell having one capacitor and one MIS transistor.
As shown in FIG. 2, the capacitor comprises a p-type silicon substrate 1, a thin insulating film 2 and a thin conductive layer 3. The thin insulating film 2 comprises: a silicon oxide film of 100 to 500 .ANG. thickness obtained by thermally oxidizing the silicon substrate; a two-layer structure having a thermal oxide film and a silicon nitride film deposited by chemical vapor deposition (to be referred to as CVD hereinafter); or the like. The thin conductive layer 3 comprises phosphorus-doped polysilicon having a low electrical resistance, or a metal (e.g., molybdenum or aluminum).
A silicon oxide film 4 of 0.2 to 1.0 .mu.m thickness and a channel stopper region 5 are formed around a pair of adjacent memory cells having a common contact hole 11 to be described later, thereby isolating the memory cells.
A MIS transistor serving as a transfer gate adjacent to the capacitor has n.sup.+ -type diffusion layers 6 as source and drain, a gate insulating film 7 and a gate electrode 8 (i.e., a word line). A bit line 10 is connected to the n.sup.+ -type diffusion layers 6 through the contact hole 11 formed in an insulating interlayer 9.
A positive voltage is applied to the thin conductive layer 3 of the capacitor with respect to the silicon substrate 1, and an n-type inversion layer is formed in the surface layer of the silicon substrate 1 below the thin insulating film 2, so that the capacitor can be charged through the MIS transistor. Charge accumulation can also be performed such that phosphorus is formed by ion implantation or thermal diffusion in the silicon substrate below the thin insulating film 2 to form an n-type conductive layer (not shown) instead of forming the n-type inversion layer.
In order to obtain a high-density 1Tr type dRAM, the memory cell area must be minimized. However, reduction of the memory cell area by the conventional method is difficult for the following various reasons.
Since a bird's beak is formed in the element isolation region in accordance with conventional selective oxidation, an element isolation width of about 1 .mu.m or less can hardly be achieved. In addition, when the memory cell area is reduced by conventional techniques, the capacitor area is also reduced. The capacitance of the memory cell and its storable charge are decreased to result in a decrease in output signal voltage and a soft error immunity. However, if the thickness of the thin insulating film 2 is decreased so as to increase the capacitance of the memory cell, the breakdown voltage is decreased. As a result, the operating voltage must be reduced and then operating margins are reduced.
In order to resolve this problem, a trench capacitor structure has been proposed wherein a trench is formed in the surface layer of the silicon substrate to comprise a capacitor, as described in Technical Digest of International Electron Devices Meeting, pp. 319-322, 1983.
According to the above reference, a thin insulating film corresponding to the thin insulating film 2 is formed in the trench, and a thin conductive layer corresponding to the thin conductive layer 3 is filled in the trench. The effective capacitor area is increased without increasing the area of the capacitor on the substrate.
When a distance between adjacent trenches is shortened in the trench capacitor structure, a punchthrough occurs to shift the charge through the silicon substrate under the oxide film 4 and the channel stopper region 5. This phenomenon is called an intercell interference, which causes storage data loss. Therefore, miniaturizing and the packing density of the memory cells are limited.